Circuit techniques for a 1.8-V-only NAND flash memory
نویسندگان
چکیده
منابع مشابه
Circuit Techniques for a 1.8-V-Only NAND Flash Memory
Focusing on internal high-voltage ( ) switching and generation for low-voltage NAND flash memories, this paper describes a switch, row decoder, and charge-pump circuit. The proposed nMOS switch is composed of only intrinsic high-voltage transistors without channel implantation, which realizes both reduction of the minimum operating voltage and elimination of the leakage current. The proposed ro...
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Features • Organization – Page size x8: 2,112 bytes (2,048 + 64 bytes) – Page size x16: 1,056 words (1,024 + 32 words) – Block size: 64 pages (128K + 4K bytes) – Device size: 2Gb: 2,048 blocks; 4Gb: 4,096 blocks; 8Gb: 8,192 blocks • READ performance – Random READ: 25μs – Sequential READ: 30ns (3V x8 only) • WRITE performance – PROGRAM PAGE: 300μs (TYP) – BLOCK ERASE: 2ms (TYP) • Endurance: 100,...
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ژورنال
عنوان ژورنال: IEEE Journal of Solid-State Circuits
سال: 2002
ISSN: 0018-9200
DOI: 10.1109/4.974549